------------------------working and simulated-------final------------------------------------------------
-- Company: 
-- Engineer: 			Sneha Nidhi
-- 
-- Create Date:    00:30:40 12/01/2010 
-- Design Name: 
-- Module Name:    RS232_TX - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
--tx from lsb to msb------------------------
entity RS232_TX is
    Port ( Clk : in  STD_LOGIC;
           Reset : in  STD_LOGIC;
           Start : in  STD_LOGIC;
           Data  : in  STD_LOGIC_VECTOR (7 downto 0);--bytes of data to tx
           EOT   : out  STD_LOGIC;--TX_RDY_i
           TX    : out  STD_LOGIC);--tx the data
end RS232_TX;

architecture Behav of RS232_TX is

type state is (Idle, StartBit, SendData, StopBit);
signal next_state,current_state : state;

--signal Data_FF    : std_logic_vector(7 downto 0);--bytes of data to tx

signal Data_count : std_logic_vector(3 downto 0);---allows max of 8 bits of data-counts the bit of data tx
signal Pulse_Width: std_logic_vector(7 downto 0);--set the freq and baud rate--time period for 1 bit to tx 
--signal StartTX    : std_logic;-- start signal for transmitter--Start
signal TX_RDY_i	: std_logic;----EOT signal
signal TD			: std_logic;--rs232 tx line --TX
--rst at 1-------------------------------------------------------------
signal rst_datacounter: std_logic;
signal rst_Pulse_Width: std_logic;
signal en_datacounter: std_logic;
constant PulseEndOfCount:std_logic_vector(7 downto 0 ):="10101101";  --to set the pulse rate to 173 

begin

rst: process(Reset,current_state,Data_count,Pulse_Width,Start,TD,TX_RDY_i)

	begin
		next_state <= current_state;
-----------no reset-----default assignment--------------- 
		rst_datacounter<='0';
		rst_Pulse_Width<='0';
		en_datacounter<='0';
		TX_RDY_i<='0';--no end of tx
		TD<='0';--no tx
--------------------------------------------------------------		
		if (Reset = '0') Then ---active low reset
			next_state<= Idle;
		else
			
			case current_state is 
----------------------------------------------------------------------------------------------------			
			when Idle =>
				TX_RDY_i<='1'; --EOT
				TD<='1';
				rst_datacounter<='1';--rst
				rst_Pulse_Width<='1';--rst
				
				if(Start ='1') Then
					next_state<= StartBit;
				end if;	
-------------------------------------------------------------------------------------------------------				
			when StartBit =>
				rst_datacounter<='1';--rst
				if (Pulse_Width=PulseEndOfCount) Then
					next_state<= SendData;
					rst_Pulse_Width<='1';--rst
				end if;
-----------------------------------------------------------------------------------------------------				
			when SendData =>
				TD <= Data(conv_integer(Data_count));--tx				
				if (Pulse_Width=PulseEndOfCount) Then --set the baud rate
					rst_Pulse_Width<='1';--rst
					if (Data_count = "0111") Then ---max 8 bit data is sent
						rst_datacounter<='1';--rst
						next_state<= StopBit;
					else 
						en_datacounter<='1';
					end if;
				end if;
-----------------------------------------------------------------------------------------------------							
			when StopBit =>
				TD <= '1';--tx the stop bit	
				if (Pulse_Width = PulseEndOfCount) Then
					next_state <= Idle;
					rst_Pulse_Width<='1';--rst
				end if;
			end case;
		end if;
	TX<=TD;
	EOT<=TX_RDY_i;
end process rst;

clking:Process (Clk)
			begin				
			if (Clk' event and Clk='1') then
				if (rst_Pulse_Width='1') then--reset
					Pulse_width <= (OTHERS => '0'); 
				else--count='1'
					Pulse_Width <= Pulse_Width+1;
				end if;
				
				if (rst_datacounter='1')then--reset
					Data_count <= (OTHERS => '0');
				else--count='1'
					if(en_datacounter='1')then
						Data_count <= Data_count + 1;
					end if;
				end if;
			current_state <= next_state;
			end if;	
	end process  clking;
end Behav;

